1. Field of the Invention
The present invention relates to a method of manufacturing a charge transfer device such as a charge-coupled device (CCD), and more particularly to a method of manufacturing a charge transfer device with a high charge transfer efficiency.
2. Description of the Prior Art
It is generally known that charge transfer devices in the form of CCDs are suitable for use as self-scanning imagers as they convert detected light into a signal charge for photogenerated charge packet storage and transfer.
As shown in FIG. 1 of the accompanying drawings, one general self-scanning solid-state CCD imager comprises an imaging area 23 composed of photosensors 21 for converting detected light into signal charge packets and vertical registers 22, and a horizontal register 25 for transferring the signal charge packets from the vertical registers 23 to an output area 24 per horizontal scanning line of television.
As shown in FIG. 2 of the accompanying drawings, the horizontal register 25 comprises an N-type impurity-diffused region or charge transfer region 31 fabricated in a silicon substrate, for example. On the charge transfer region 31, there are disposed a gate insulating film 32 with first and second horizontal transfer electrodes 33, 34 disposed thereon as first and second polycrystalline silicon layers. These two horizontal transfer electrodes 33, 34 are combined in an array, and a plurality of such arrays are successively arranged horizontally. An interlayer insulation film 35 is interposed between the first and second horizontal transfer electrodes 33, 34 of each pair. Each pair of two adjacent horizontal transfer electrodes 33, 34 serves as one transfer stage. Signal charge packets are successively transferred in one direction when two-phase drive pulses in opposite phase are applied to alternate transfer stages.
When the same potential is applied to the transfer electrodes 33, 34, a so-called fringing electric field develops underneath the interlayer insulation films 35 between the transfer electrodes 33, 34. The fringing electric field generates potential dips or potential pockets d beneath the interlayer insulation films 35, preventing the charge packets from being completely transferred.
One conventional configuration to avoid the above potential dips is shown in FIG. 3 of the accompanying drawings. In FIG. 3, a P-type impurity such as boron (B) is diffused into the charge transfer region 31 below the second transfer electrodes 34, for example, creating P-type impurity-diffused regions 36. In the solid-state CCD imager shown in FIG. 3, when the same potential is applied to the transfer electrodes 33, 34, the potential below the second transfer electrodes 34 is lower than the potential below the first transfer electrodes 33. The lower potential is referred to as an "implanted barrier" in general. Consequently, no potential dips occur beneath the interlayer insulation films 35 between the transfer electrodes 33, 34, with the result that the charge packets can be transferred with an improved charge transfer efficiency.
As the size of integrated circuit elements of solid-state CCD imagers becomes smaller and smaller, it is more difficult for the conventional solid-state CCD imager scheme shown in FIG. 3 to keep a good charge transfer efficiency while maintaining a desired dynamic range for the output signal because of the relationship between the amount of charge packets to be handled and the fringing electric field.
According to a known solution, an impurity is diffused below the first and second transfer electrodes 33, 34 with different densities along the direction in which the charge packets are transferred, creating a staircase-shaped potential gradient below the first and second transfer electrodes 33, 34 (see, for example, Japanese laid-open patent publication No. 2-280375).
To obtain such a staircase-shaped potential gradient, it has been proposed to form a photoresist mask over the charge transfer region 31 before the first and second transfer electrodes 33, 34 are formed, for the purpose of achieving different impurity densities in the surface of the charge transfer region 31 below the first and second transfer electrodes 33, 34.
More specifically, as shown in FIG. 4A of the accompanying drawings, after the gate insulating film 32 is disposed on the N-type charge transfer region 31, a photoresist film 37 is deposited on the entire surface of the gate insulating film 32. Thereafter, openings 37a are formed in the photoresist film 37 in portions of its areas over which the first and second transfer electrodes 33, 34 are to be formed. Subsequently, an N-type impurity is ion-implanted into the N-type charge transfer region 31, forming high-density N-type impurity-diffused regions 38 in the surface of the charge transfer region 31.
Then, as shown in FIG. 4B of the accompanying drawings, the photoresist film 37 is removed, and thereafter first transfer electrodes 33 are formed as a first polycrystalline silicon layer on the gate insulating film 32. As shown in FIG. 4C of the accompanying drawings, an interlayer insulation film 35 is selectively formed on the first transfer electrodes 33, after which a second polycrystalline silicon layer is deposited on the surface formed so far. The second polycrystalline silicon layer is then patterned into second transfer electrodes 34. The N-type impurity-diffused regions 38 are now positioned below portions of the first and second transfer electrodes 33, 34.
However, the positional alignment between the N-type impurity-diffused regions 38 and the first transfer electrodes 33 may suffer errors depending on the accuracy of the photoresist mask registration. Therefore, the above fabrication process tends to bring about characteristic degradations particularly in solid-state CCD imagers with smaller integrated circuit elements.